Commit Graph

92 Commits

Author SHA1 Message Date
Satoshi Niwa
1b279c6b5d Rename arch variant goldmont-without-xsaves to goldmont-without-sha-xsaves
Bug: 314243939
Test: Build an image with TARGET_ARCH_VARIANT:=goldmont-without-sha-xsaves
Change-Id: I3d3147e12093fecbcc3873c44a47b1f778c09191
2024-01-24 16:31:27 +09:00
Satoshi Niwa
88fc7ad3a8 Add a new x86(_64) arch variant "goldmont-without-xsaves"
Its target arch is goldmont, but without xsaves support.
It can build images that run on old Intel/AMD CPUs as well as new CPUs.

Bug: 314243939
Test: Build an image with TARGET_ARCH_VARIANT:=goldmont-without-xsaves
Change-Id: I9c4bfd3928511f5b4a075f9a9337db6e1270a765
2023-12-14 17:47:56 +09:00
Evgenii Stepanov
3148fe365b Add armv9-a arch variant.
Bug: b/263283855
Test: none
Change-Id: I0e9fd48305ad1a26a708ecb2f0d3e7a07e14dbc8
2023-03-05 14:38:12 -08:00
Ryo Hashimoto
05f2b52d16 Add arch variants for Intel Atom CPUs
Bug: 259201836
Test: Build aosp_x86_64-eng with modified
build/make/target/board/generic_x86_64/BoardConfig.mk

Change-Id: Ide469d4aaa722602dbcc797cf6518fd20d24764c
2022-11-16 18:28:15 +09:00
Colin Cross
dac728895d Add initial files for aosp_riscv64 target
Add barebones files to support building for a riscv64 target.

Bug: 250918230
Test: lunch aosp_riscv64-userdebug && m ALLOW_MISSING_DEPENDENCIES=true nothing
Change-Id: I61e6ecf6706b7682c77b07e6593d78c7d1eaef39
2022-10-05 12:04:31 -07:00
Tamas Petz
1c879b8822 Add armv8-a-branchprot arch variant
This empty file is required to be present.

Test: fvp_mini-eng* builds and boots on FVP

*: with TARGET_ARCH_VARIANT := armv8-a-branchprot

Change-Id: I689033f16663822e263f45ab5e46c9f120c9dca0
2021-01-28 17:10:24 +01:00
Raphael Gault
b817bb161d Add new armv8-2a-dotprod arch variant support.
This patch introduces the .mk file required to support build for the new
armv8-2a-dotprod Arm64 arch variant. The file just needs to be present
but does not require to contain anything.

Test: test-art-target on Pixel 4.

Change-Id: I4b6a1e306f9819cf31cd556351bd3e8cf08e2537
2020-09-16 14:53:06 +00:00
Elliott Hughes
2e6e73bb01 Remove unused BoardConfig variables.
Determined via codesearch.

Test: treehugger
Change-Id: I5138e1b2294d39e11b46f9e1751c41b842c1743b
2019-07-18 21:43:38 -07:00
Colin Cross
88e38f01ba Merge "Add x86 AVX2 and AVX512 supported architectures" 2019-03-20 06:22:22 +00:00
Benjamin Gordon
b8bf92e6b8 Add stoney ridge x86 variant
Bug: 124445930
Test: compile and deploy to grunt
Change-Id: Ia73c27f7ce9ca9031e733a3754ffbb2fabeae4d0
2019-02-14 11:03:00 -07:00
Shalini Salomi Bodapati
0b33968b31 Add x86 AVX2 and AVX512 supported architectures
Bug: 123376719
Test: m checkbuild
Change-Id: I74c7a63bbaba993eeb8bdd8c663ffa142c908279
Signed-off-by: Shalini Salomi Bodapati <shalini.salomi.bodapati@intel.com>
(cherry picked from commit f327f5f3f5d03471d69e757fe33899a7fd653f18)
2019-01-30 02:34:05 +00:00
Dan Willemsen
53d62fed72 Bump the remaining 32-bit arm configs to require neon
Stop using armv7-a without neon for 32-bit unbundled apps, and update
generic_x86_arm to match the cuttlefish configuration that includes
neon.

Test: treehugger
Change-Id: Ieb6a2106655803a8ca609907c12168e628ee1b85
2019-01-23 22:27:33 -08:00
Miao Wang
62c2390a55 Correctly configure armv8-2a for 32-bit
Bug: 119681317
Test: mm
Test: CtsRenderscriptTestCases
Change-Id: I455c94948430d3cc2dd320cce830ae18be6a93cd
2018-11-27 14:05:48 -08:00
Isaac Lee
ead02eb87d Enable armv8-2a supporting on 2nd arch. variant
Newer cores are implementing armv8-2a ISAs.
Enabling 2nd arch. variant to support for new type of cores.

Test: set TARGET_2ND_ARCH_VARIANT := armv8-2a, build without warnings and not ignore armv8-2a
BUG: 118414869
Change-Id: I1cd64ab0ad9b253ec3d109ebd1dbc7882011ce77
2018-11-13 17:31:28 +08:00
Christopher Ferris
47b29ea339 Add support for cortex-a55/cortex-a75.
Bug: 78133793
Bug: 78242072

Test: Builds for target.
Change-Id: I98d638017f943083d3832ec2211333c48f07caf2
Merged-In: I98d638017f943083d3832ec2211333c48f07caf2
(cherry picked from commit ce7bf678f2)
2018-05-11 00:43:19 +00:00
Dan Willemsen
dd3a27394f Remove armv5te
This architecture only existed for unbundled use, but even the NDK is
removing support in their r17 release, so just remove support for it.

Test: build/soong/build_test.bash -only-config
Test: check buildserver configs, I don't see anything still using armv5
Change-Id: Ic183b510c9ada94438bd4cc2b9362fa438a29ced
2018-01-08 15:26:16 -08:00
Colin Cross
6cdc5d20f3 Update references to build/core to build/make/core
sed -i -e 's"\([^/]\)build/core"\1build/make/core"g' $(git grep -l build/core)

Test: m checkbuild
Change-Id: Idf3a2fed79aee5d2c07bd8e42f0c0660f253ddc2
2017-10-20 12:49:28 -07:00
Isaac Chen
f5af850a29 Revert "Revert "Build support for 32-bit armv8-a""
This reverts commit 7de79cbeaf.

Fixed CTS build issue by adding -march=armv7-a in cts/tests/tests/os/jni/Android.mk since the library built here needs/uses instruction (swp) obsolete in ARMv8.

Bug: 64964151
Test: lunch aosp_arm64-userdebug; make -j cts
      lunch aosp_x86-userdebug; make -j cts
      lunch aosp_sailfish-userdebug; make -j cts
      lunch aosp_bullhead-userdebug; make -j cts

Change-Id: Ic3a121600da8e2a9a2d5176b9680cd18ce457959
2017-08-23 10:58:57 +00:00
Tobias Thierer
7de79cbeaf Revert "Build support for 32-bit armv8-a"
This reverts commit 0daa78eef4.

Reason for revert: Broke the build for some targets (including marlin and angler).

$ make cts
build/core/combo/TARGET_linux-arm.mk:43: kryo is armv8-a.
build/core/combo/TARGET_linux-arm.mk:45: TARGET_2ND_ARCH_VARIANT, armv7-a-neon, ignored! Use armv8-a instead.
[...]
cts/tests/tests/os/jni/android_os_cts_CpuInstructions.cpp:88:20: error: instruction requires: armv7 or earlier
    asm volatile ( "swp r0, r0, [%0]" : "+r"(ptr) : : "r0" );
                   ^
<inline asm>:1:2: note: instantiated into assembly here
        swp r0, r0, [r1]
        ^

Change-Id: I65a91ed5a4461eca6646df13642a87a5c37d6c85
2017-08-21 15:03:16 +00:00
Isaac Chen
0daa78eef4 Build support for 32-bit armv8-a
Overwrite TARGET_(2ND_)ARCH_VARIANT as armv8-a if
TARGET_(2ND_)CPU_VARIANT is set to some known armv8-a core like
cortex-a53, cortex-a73, kryo, denver64 etc.

For clang, -march is ignored if -mcpu is set to specific core so this
change doen't impact the objects built for armv7-a-neon/some_armv8_core
since it's treated as armv8-a/some_armv8_core.

Bug: 62895439
Test: Built modified aosp_arm64 with armv8-a as its TARGET_2ND_CPU_ARCH
      and generic as its TARGET_2ND_CPU_VARIANT successfully.
      "lunch hikey-userdebug; make" and verify TARGET_2ND_ARCH_VARIANT
      is overwritten.

Change-Id: If4260cf397783b5f56c4fd432615f4676429a1d3
2017-08-10 16:13:22 +08:00
Duane Sand
47b57e6bd2 Allowing pairing mips64r6 with mips32r1 and r2
On mips64r6 builds, the shell variable ARCH_MIPS_REV6 is not
cleared before compiling 2nd arch parts.  This bug is harmless when
2nd arch is mips32r6 but it omits needed mips-specific assembly
files when compiling libagl and libpixelflinger for mips32r1 or r2.

Clearing the variable is impractical.  Using TARGET_2ND_ARCH qualifiers
would work, but Arm and x86 use a simpler method with distinct ARCH_ARM
and ARCH_ARM64 symbols.  ARCH_MIPS_REV6 is used in two places.
Both controll 32-bit parts only, so neither place needs adjustment.

Change-Id: Id1ea5e8b6f8666d9df219fa9ef41834bd31f5dd8
2016-08-10 12:13:30 -07:00
Dan Willemsen
056609ccfe Remove unnecessary variables
These are all either recently unused due to the removal of CFLAGS/etc,
or have been exported by Soong and are no longer necessary.

Change-Id: I5930d43fda21acc8202b3d8ea010fbefb6ae4cf1
2016-05-25 21:23:20 -07:00
Dan Willemsen
19b7692496 Merge "Add a 32-bit x86_64 arch variant" 2016-05-11 00:35:59 +00:00
Dan Willemsen
9826900aea Do not apply -Wl,--fix-cortex-a8 to Cortex-A9
Change-Id: I11d380163423cb4aa0fee60ecbaa1e38fa5143a1
2016-05-10 15:36:58 -07:00
Dan Willemsen
04aa521eca Add a 32-bit x86_64 arch variant
The current 32-bit configuration for generic x86_64 targets inherits some
variables (SSE4 support) from the 64-bit configuration, and overrides
the make variables used for other configurations (SSSE3). Ideally, these
would be using different variables, but until then, unify the
configuration for x86_64 targets so that everything is consistent.

Bug: 28694691
Change-Id: I47e67299d4c632e7491d7e73dc0fc6480ef08006
2016-05-10 14:15:41 -07:00
Olof Johansson
b044f082e6 Merge "sandybridge setup: no AES_NI, AVX, MOVBE" 2016-02-29 23:27:04 +00:00
Alex Light
bdfeb3e760 Mark the cortex-{a7,a53,a53.57} chips as supporting LPAE
Bug: 27340895
Bug: 27324856

Change-Id: Id3994c6d334c8bb673fc3849550f591136a8dd6a
2016-02-24 13:54:11 -08:00
Olof Johansson
593eb7b8d7 sandybridge setup: no AES_NI, AVX, MOVBE
Sandy Bridge actually doesn't have all of these options. For example AVX is only
available on the higher-end SKUs (not on Celeron G550).

Change-Id: Ib595a9a6b464626d0c88525c6aaa4d69176645cc
2016-02-23 20:42:42 -08:00
Christopher Ferris
9937e7b2a3 am 76ec0c4c: Merge "Set mcpu targets based on cpu variant."
* commit '76ec0c4c53aab6fca7af1badab882518962a9755':
  Set mcpu targets based on cpu variant.
2015-09-25 16:35:56 +00:00
Christopher Ferris
561b4c1995 Set mcpu targets based on cpu variant.
Make cortex-a53 and cortex-a53.a57 use cortex-a7.

Change-Id: I89d5b3f044c867ec99aae319eafc33f2edf1f9f2
2015-09-24 13:59:33 -07:00
Ying Wang
91a38d07d0 am 68787b3d: am bbaeaa58: Merge "Configure synci generation explicitly"
* commit '68787b3d1e0b230f3fd812759be03736f73daaf4':
  Configure synci generation explicitly
2015-07-02 06:39:10 +00:00
Tim Murray
b6b20af512 Add support for cortex-a53 variants when building 64-bit.
Change-Id: I3f1fb5dbde731d9c3d6db26a46bc7f0f54d8e071
2015-06-11 16:02:13 -07:00
Chris Dearman
ab3a5f490c Configure synci generation explicitly
The default for synci generation is compiler version dependent

Change-Id: I3f94cabd98c45aaa4e5149e8bb050dc47efa61ca
2015-04-30 13:22:16 -07:00
Bernhard Rosenkränzer
4da707176b Don't use -Wl,--fix-cortex-a8 for Cortex A7, A9, A15, Krait or Denver
-Wl,--fix-cortex-a8 is a workaround for an Erratum in Cortex-A8
processors. It slightly increases code size and decreases performance,
and there's no point in using it on non-A8 CPUs.

Instead of forcing it unconditionally, use it when targeting
Cortex-A8 or generic armv7-a (which might or might not be A8).

Change-Id: Ifa59765d380445237edccfe5440a67b3ba1e459a
Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
2015-03-25 17:21:02 +01:00
Mingwei Shi
357778de34 Update x86_64 minimal ISA instruction set
Change-Id: I3ca7f8a0799e6aef09ab1dfb719d218c7338ebf8
Signed-off-by: Mingwei Shi <mingwei.shi@intel.com>
2015-03-12 22:45:27 +08:00
Alexander Ivchenko
6bbaee0682 Rename core/combo/arch/x86/x86-atom.mk to core/combo/arch/x86/atom.mk.
Otherwise wrong set of memory/string functions is chosen when building atom
image (in Bionic we have libc/arch-x86/atom/atom.mk). Plus this naming is
consistent with other x86 architectures.

Change-Id: I21e899534e7ce10530474a22ceba770422b39d8d
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
2014-12-03 22:41:10 +03:00
Chih-hung Hsieh
51e55c1d22 Revert "Continue to use march=i686 before fix of g++ ICE."
This reverts commit f70f009ca8.

Change-Id: I3e1b18cf342e747c8a8405f1fc2513e5ebafc4b6
2014-10-30 01:55:45 +00:00
Chih-Hung Hsieh
f70f009ca8 Continue to use march=i686 before fix of g++ ICE.
BUG: 18174291
BUG: 18171557
Change-Id: Ica9e420e3cc1904a4298e2ab1c6201a254cbf6d1
2014-10-29 14:46:15 -07:00
Ian Rogers
e270873407 Specify -mcpu=krait for clang.
Change-Id: I64682cddf57246341c1727ca16c56f7ce0c6fd0a
2014-10-28 15:50:02 -07:00
Chih-Hung Hsieh
c248fa3e01 Raise x86 arch requirement to prescott.
Atomic functions used in external/libcxx/include/atomic when compiled with Clang
will require intrinsic functions exist only for prescott or newer CPUs.

BUG: 17530542
Change-Id: I0c9660ed2ffa75b940981eb8165d88934b39aec5
2014-10-22 15:25:49 -07:00
Ian Rogers
63e551f0ae Move definition of -D__ARM_FEATURE_LPAE=1 cflag to top-level.
LPAE indicates better instructions can be used when atomicity guarantees are
needed. However, LPAE's presence isn't advertised by clang/GCC. We fake an
ARM feature to advertise its presence on architectures where it is.
Also, add a TODO documenting that cortex-a15 is not the correct CPU variant
for krait.

Change-Id: I02a1248025c32d94eca0bc8a249dc524f1ac9c36
2014-10-15 15:44:16 -07:00
Alexander Ivchenko
ae2d47a47f Remove "-mstackrealign" option from all x86 builds.
For ndk docs change, please refer to:
https://android-review.googlesource.com/#/c/110100/

Change-Id: I8428e7a979eb02441066aeeee43ce693d4d0dc8d
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
2014-10-13 19:08:01 +04:00
Varvara Rainchik
2d645ab323 Add missing flags to x86 (both 32- and 64-bit) arch variants.
Delete x86_64-atom.mk as we don't support 64-bit on old Atom.

Change-Id: I0b9ab61cd9b840f32c30059cb3ba9704c733c42a
Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
2014-08-04 18:46:14 +04:00
Duane Sand
6bab974cdc [MIPSR6] Add mips64r6 and mips32r6 targets
Add mips64r6 target and corresponding mips32r6 target.
Defaults remain as mips64r2 and mips32r2.

Apply -FP64A codegen subsetting to mips32r6 only.
Access FR=0 odd-numbered 32-bit float regs only via
double-prec even-numbered regs, not by single-prec ops.

Change-Id: I1740a6c658304b6c41242be58d68753e6f171658
2014-07-24 11:19:21 -07:00
Duane Sand
6670e24aed [MIPS] Unite mipsel and mips64el 4.9 gcc toolchains
Use 4.9 mips64el toolchain for both 64- and 32-bit builds.
Tell ld when 32-bit links are required.
Override 4.9's changed defaults for mips floating point
register use, to get same assembler rules as 4.8 and earlier.

Also: drop unused  soft-fp build targets, cleanout redundant
compiler options, and remove extraneous Android.mk file.

Change-Id: I86f1075266349edb2b08a7709b9f5472d8cfda32
2014-07-23 14:16:00 -07:00
Andrew Boie
155fc8b5fe add silvermont x86 architecture
This is used for Baytrail targets.

Change-Id: I5a2fa6dbb8217a326ee09f5ea434885718ab3f0c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
2014-04-30 01:23:25 +08:00
Shu Zhang
453afb242c Specify -mcpu=cortex-a15 for denver CPU variants.
Change-Id: Ic27484c92a48b45148021a61420ffdd55a9dd945
2014-03-24 16:19:50 +08:00
Ying Wang
de9955c35e Select the arch_variant_cflags for the 2nd arch.
Change-Id: Id2f9d7073a4aae3ba0fe5e5464045761f4d42b4e
2014-02-07 10:44:10 -08:00
Chris Dearman
1efd9e462a [MIPS64] Add mips64 target
Change-Id: Ice1621101c0d5a3314db288542ca8020e3f406bf
Signed-off-by: Duane Sand <duane.sand@imgtec.com>
2014-02-05 19:07:57 -08:00
Colin Cross
ec14ce578b remove 2nd arch from ARCH_ARM_* defines
Users of ARCH_ARM_* defines don't care about first vs. second arch,
set ARCH_ARM_* regardless of which arch is arm.

Change-Id: I2ae83ec5c3f839ff91a0e352c95d76ec2cbd5dc5
2014-02-04 19:44:09 -08:00