These are all either recently unused due to the removal of CFLAGS/etc,
or have been exported by Soong and are no longer necessary.
Change-Id: I5930d43fda21acc8202b3d8ea010fbefb6ae4cf1
Delete x86_64-atom.mk as we don't support 64-bit on old Atom.
Change-Id: I0b9ab61cd9b840f32c30059cb3ba9704c733c42a
Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
ARCH_X86_HAVE_MMX, ARCH_X86_HAVE_SSE, ARCH_X86_HAVE_SSE2,
and ARCH_X86_HAVE_SSE3 were all always on. There are no longer any makefiles
or code that are conditional on any of these, so let's just remove them
rather than encourage anyone to mess with knobs that don't work.
Change-Id: I5ee095e8041eecff4554ad4801894fbfca69093f
Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com>
Author: Andrew Boie <andrew.p.boie@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Currently, x86 target only has generic i686 and x86-atom
as arch variants. This patch adds the ability to have
more than two arch variants. Defining a new arch variant
is similiar to ARM targets, by adding a new file in
core/combo/arch/x86. These files also define what
capabilities the targeting CPU has (e.g. having SSE2,
SSE3, etc.).
We define arch variants for Sandy Bridge, Ivy Bridge,
Haswell; upcoming arches can be easily added to this
set with future patches.
Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
