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12 Commits

Author SHA1 Message Date
Elliott Hughes
2e6e73bb01 Remove unused BoardConfig variables. 
Determined via codesearch.

Test: treehugger
Change-Id: I5138e1b2294d39e11b46f9e1751c41b842c1743b
 2019-07-18 21:43:38 -07:00
Colin Cross
88e38f01ba Merge "Add x86 AVX2 and AVX512 supported architectures" 2019-03-20 06:22:22 +00:00
Benjamin Gordon
b8bf92e6b8 Add stoney ridge x86 variant 
Bug: 124445930
Test: compile and deploy to grunt
Change-Id: Ia73c27f7ce9ca9031e733a3754ffbb2fabeae4d0
 2019-02-14 11:03:00 -07:00
Shalini Salomi Bodapati
0b33968b31 Add x86 AVX2 and AVX512 supported architectures 
Bug: 123376719
Test: m checkbuild
Change-Id: I74c7a63bbaba993eeb8bdd8c663ffa142c908279
Signed-off-by: Shalini Salomi Bodapati <shalini.salomi.bodapati@intel.com>
(cherry picked from commit f327f5f3f5d03471d69e757fe33899a7fd653f18)
 2019-01-30 02:34:05 +00:00
Colin Cross
6cdc5d20f3 Update references to build/core to build/make/core 
sed -i -e 's"\([^/]\)build/core"\1build/make/core"g' $(git grep -l build/core)

Test: m checkbuild
Change-Id: Idf3a2fed79aee5d2c07bd8e42f0c0660f253ddc2
 2017-10-20 12:49:28 -07:00
Dan Willemsen
056609ccfe Remove unnecessary variables 
These are all either recently unused due to the removal of CFLAGS/etc,
or have been exported by Soong and are no longer necessary.

Change-Id: I5930d43fda21acc8202b3d8ea010fbefb6ae4cf1
 2016-05-25 21:23:20 -07:00
Olof Johansson
593eb7b8d7 sandybridge setup: no AES_NI, AVX, MOVBE 
Sandy Bridge actually doesn't have all of these options. For example AVX is only
available on the higher-end SKUs (not on Celeron G550).

Change-Id: Ib595a9a6b464626d0c88525c6aaa4d69176645cc
 2016-02-23 20:42:42 -08:00
Mingwei Shi
357778de34 Update x86_64 minimal ISA instruction set 
Change-Id: I3ca7f8a0799e6aef09ab1dfb719d218c7338ebf8
Signed-off-by: Mingwei Shi <mingwei.shi@intel.com>
 2015-03-12 22:45:27 +08:00
Varvara Rainchik
2d645ab323 Add missing flags to x86 (both 32- and 64-bit) arch variants. 
Delete x86_64-atom.mk as we don't support 64-bit on old Atom.

Change-Id: I0b9ab61cd9b840f32c30059cb3ba9704c733c42a
Signed-off-by: Varvara Rainchik <varvara.rainchik@intel.com>
 2014-08-04 18:46:14 +04:00
Andrew Boie
155fc8b5fe add silvermont x86 architecture 
This is used for Baytrail targets.

Change-Id: I5a2fa6dbb8217a326ee09f5ea434885718ab3f0c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
 2014-04-30 01:23:25 +08:00
Elliott Hughes
d3f00c162b Remove useless x86 options that were always hardcoded on. 
ARCH_X86_HAVE_MMX, ARCH_X86_HAVE_SSE, ARCH_X86_HAVE_SSE2,
and ARCH_X86_HAVE_SSE3 were all always on. There are no longer any makefiles
or code that are conditional on any of these, so let's just remove them
rather than encourage anyone to mess with knobs that don't work.

Change-Id: I5ee095e8041eecff4554ad4801894fbfca69093f
 2013-10-04 11:45:06 -07:00
Pavel Chupin
fd82a49e04 x86_64: Adding new target 
Add x86_64 Android builds. Compiler is expected to be able to understand
-m64 code generation option.

Change-Id: I99e7337c5a5766afc5e528a481bd21631ff44dd5
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
 2013-10-02 20:58:54 +04:00