This patch completes the support for AArch64. It adds the last few
tweaks that will enable a AArch64 build of bionic.
Please note that though AArch64 uses the new kernel infrastructure,
where the userspace exported headers live in uapi folders, we still
need to include "kernel/common" in the include search path
(take a look at external/kernel-headers/uapi/asm-generic/signal-defs.h).
Also remove the relro linker flags for now as they crash the foundation
model.
Change-Id: Ie2fa8c1056c84dc15fec4469f2d65b8d0c5e712b
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
In 4f2f16da14, we added
-Wl,--warn-shared-textrel to TARGET_GLOBAL_LDFLAGS. This generated
a warning whenever we created a shared library with a text
relocation. At the time, we wrote:
=====
Emit a warning when the static linker detects a shared library
has text relocations. Text relocations make it harder to
share pages across processes, and make it harder to use
certain memory protection features in, for example, SELinux.
This warning will turn into an error in a future change
(via --fatal-warnings)
=====
All code which uses text relocations has either been fixed, or
we've temporarily worked around the issue so the code can still
compile.
Enable --fatal-warnings.
Bug: 11353056
Change-Id: I2f2c65352166ef0a96f54858de1556f0290fe306
ARCH_X86_HAVE_MMX, ARCH_X86_HAVE_SSE, ARCH_X86_HAVE_SSE2,
and ARCH_X86_HAVE_SSE3 were all always on. There are no longer any makefiles
or code that are conditional on any of these, so let's just remove them
rather than encourage anyone to mess with knobs that don't work.
Change-Id: I5ee095e8041eecff4554ad4801894fbfca69093f
Add x86_64 Android builds. Compiler is expected to be able to understand
-m64 code generation option.
Change-Id: I99e7337c5a5766afc5e528a481bd21631ff44dd5
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
For supporting loading a custom key type provider, add a -providerClass
argument that loads the selected JCE at the front of the provider list.
Change-Id: I3df16f7c570d36e08806b614d6f30c41cb117565
The PKCS#8 PrivateKeyInfo structure has the algorithm OID encoded right
before the actual key octet stream is encoded. Use Bouncycastle to read
the OID for creation with the key factory.
This aids in the creation of custom key types that are backed by
hardware devices (e.g., HSMs) and have their own assigned OIDs.
Change-Id: If5d8fe07bc157e9bb5a3fb5f99091e924143105f
Author: Negreanu Marius Adrian <adrian.m.negreanu@intel.com>
Author: Andrew Boie <andrew.p.boie@intel.com>
Author: Daniel Leung <daniel.leung@intel.com>
Currently, x86 target only has generic i686 and x86-atom
as arch variants. This patch adds the ability to have
more than two arch variants. Defining a new arch variant
is similiar to ARM targets, by adding a new file in
core/combo/arch/x86. These files also define what
capabilities the targeting CPU has (e.g. having SSE2,
SSE3, etc.).
We define arch variants for Sandy Bridge, Ivy Bridge,
Haswell; upcoming arches can be easily added to this
set with future patches.
Change-Id: Iafbce10d205e860738db4a216ff603f9a84d7311
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
With this change, modules introduced by LOCAL_REQUIRED_MODULES will be
split by host/target: target modules only depend on target modules and
host modules only depend on host modules.
Bug: 9303948
Change-Id: I4078a7983aa3c00e99534f3f170dfe4b66b12287
